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5
FN2809
.8
October
16,
200
8
ENPOREG
R.ENPOREG
ENPHAC
FIGURE 1. BLOCK DIAGRAM OF THE HSP45106
'0'
A(2:0)
MOD(2:1)
OES
BINFMT
OEC
R.ENPHAC
28
16
R
E
G
R.ENOFREG
R.ENCFREG
R.ENPHAC
R.ENTIREG
R.INHOFR
R.INITPAC
R.PMSEL
R.PACI
R.INITTAC
ENOFREG
ENCFREG
ENTIREG
INHOFR
INITPAC
PMSEL
PACI
INITTAC
CLK
D
E
C
O
D
E
PHEN
MSCFEN
LSCFEN
MSOFEN
LSOFEN
MSTIEN
LSTIEN
WR
CS
C(15:0)
ENCODER
R.ENPHAC
R.ENCFREG
A
D
E
R
R.PMSEL
R.INITPAC
R.INHOFR
R.ENOFREG
A
D
E
R
R.INITTAC
R.ENTIREG
R.ENPOREG
A
D
E
R
32
A
D
E
R
16
MSBs
PHEN
PHASE
PHASE INPUT
CENTER
OFFSET
TIMER
REGISTER
32
PHASE OFFSET
3
13
16
'0'
32
CENTER
REGISTER
32
'0'
32
16
LSBs
PHASE OFFSET
FREQUENCY
ADDER
32
PHASE
REGISTER
32
TICO
32
'0'
LSCFEN
LSOFEN
MSTIEN
LSTIEN
PHASE
ACCUMULATOR
SECTION
TIMER
ACCUMULATOR
SECTION
32
OFFSET FREQUENCY
REGISTER
R.PACI
16
INPUT SECTION (DISCRETE CONTROL INPUT SIGNALS
AND PROCESSOR CONTROL INTERFACE)
MSB CENTER
LSB
16
MSB OFFSET
LSB OFFSET
MSB TIMER INCREMENT
LSB TIMER
16
FREQUENCY
INCREMENT
REGISTER
ADDER
FREQUENCY
INCREMENT CLK
FORMAT
CONTROL
ADDRESS
16 COS
16 SIN
OUTPUT
CONTROL
/
16
/
16
SIN/COS
SIN/COS ARGUMENT
/
28
/
20
ACCUMULATOR
DACSTRB
COS(15:0)
SIN(15:0)
WR
>
16
0
1
MUX
CLK
R
E
G
>
CLK
R
E
G
>
CLK
R
E
G
>
R
E
G
>
CLK
R
E
G
>
CLK
R
E
G
>
R
E
G
>
R
E
G
>
R
E
G
>
R
E
G
>
R
E
G
>
R
E
G
>
WR
R
E
G
>
R
E
G
>
R
E
G
>
CLK
0
1
MU
X
0
1
MUX
0
1
MUX
CLK
INPUT REG (16)
FREQUENCY INPUT
REG (16)
CENTER
FREQUENCY
INPUT REG (16)
FREQUENCY INPUT
REG (16)
FREQUENCY
INPUT REG (16)
INCREMENT INPUT
REG (16)
DECODE
ROM
PAR/SER
TEST
3
HSP45106
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